1. Technical Field
The present invention relates to a performance board and a cover member. Particularly, the present invention relates to the performance board which is attached to a test head in a semiconductor test apparatus so as to be an interface between the test head and a device under test, and relates to a cover member which is used while being attached to the performance board.
2. Related Art
In usual semiconductor test apparatus, various tests targeting various devices under test are executed. Here, a semiconductor test apparatus is formed by combining a handler which accommodates, conveys and mounts the devices under test, a test head which forms an electrical connection to the devices under test and a mainframe which controls the whole operation and so forth. Additionally, the semiconductor test apparatus has a structure which can partially replace components in accordance with a target and a content of a test to be executed. Moreover, in the semiconductor test apparatus, an environmental test is also executed in addition to tests using various test signals, which operates the devices under test while the temperature environment is changed. Here, a high-temperature test and a low-temperature test which are executed as cooling or heating the devices under test will be generically described as “temperature test.
When a temperature test is executed in a semiconductor test apparatus, the temperature of a device under test should be kept a predetermined set temperature. Thus, a thermostatic chamber enclosed by a high-adiathermic material is provided in the semiconductor test apparatus, and then a test is executed while the device under test is accommodated in the thermostatic chamber. However, when a semiconductor is tested, it is also required that the device under test is connected to an electronic circuit disposed outside the thermostatic chamber. Therefore, various structures being capable of satisfying both of the adiathernanous and the electrical connection have been suggested.
Particularly, in the low-temperature test, the temperature of a part of the semiconductor test apparatus facing the cooled thermostatic chamber is decreased than that of the other portions. When such portion takes the air, dew condensation would be formed, and then the electrical circuit is wet due to the dew condensation, therefore electrical characteristic is changed thereby accuracy of the test is reduced. Thus, for the semiconductor test apparatus executing the low-temperature test, various suggestions with respect to structures or methods for preventing the dew condensation from forming have been provided.
A test apparatus including a structure that interfaces to devices under test are collectively accommodated in a high/low temperature chamber has been described as, for example, in 1) Japanese Patent Application Publication No. H7-260879. Thereby the temperature of the devices under test can be kept a predetermined test temperature, and the temperature within the high/low temperature chamber is prevented from affecting the test head of the semiconductor test apparatus.
In addition, a structure that a under surface of a thermostatic chamber providing a temperature environment of the devices under test is sealed has been described as, for example, in 2) Japanese Patent Application Publication No. 2000-147053. Thereby the dew condensation formed on the test head side can be prevented from forming when the interior of the thermostatic chamber is cooled.
Moreover, a structure that a space is provided below the base of a kind replacement section on which the devices under test are mounted has been suggested as, for example, in 3) Japanese Patent Application Publication No. 2000-147055. Thereby the temperature in the thermostatic chamber can be prevented from affecting the test head.
However, the structure described in 1) requires a large space between a conversion board attached to the test head and sockets on which devices under test are mounted. Therefore, the semiconductor test apparatus which can be tested are limited.
The structure described in 2) has a structure dedicated to a motherboard forming an interface on the test head side. Therefore, the structure of the thermostatic chamber which can be combined with the motherboard is limited, so that the semiconductor test apparatus's own structure should be changed.
Moreover, the structure described in 3) requires a large space between the test head and the thermostatic chamber. Therefore, the specification of the semiconductor test apparatus being capable of embodying the structure is limited.
As described above, there has been a problem that the structures of a semiconductor test apparatus which executes a temperature test and those components tend to be large. In addition, there also has been a problem that a cost is increased because such as motherboard's own structure should be changed.